A flash memory employing a NOR-type cell array (hereinbelow, referred to as a NOR-type flash memory) operates at a faster speed relative to a NAND-type flash memory. For this reason, a NOR-type flash memory is often used in a high frequency system.
FIG. 1 is a cross sectional view of a memory cell for a NOR-type flash memory device. The NOR-type flash memory device is constructed of N-type source region 3 and N-type drain region 4 formed in P-type substrate (or well) 2. The regions 3 and 4 are isolated from each other through a channel region that is defined in substrate 2. Floating gate 6 is formed over the channel region through thin insulating film 7. Insulating film 7 is under about 100 .ANG. thick. Insulating film 9 is formed on floating gate 6 isolating control gate 8 from floating gate 6. Insulating film 9 is preferably an Oxide-Nitride-Oxide (O--N--O film). Source region 3 is connected to source voltage Vs. Drain region 4 is connected to drain voltage Vd. Control gate 8 is connected to gate voltage Vg. Substrate 2 is connected to bulk voltage Vd.
During programming, a selected memory cell is programmed by means of a hot electron injection between the channel region and floating gate. To induce the hot electron injection, the source and substrate are held to a ground voltage while a high voltage (e.g., Vg=10V) is applied to the control gate and a voltage, 5V through 6V, is provided to the drain. After programming, a threshold voltage of the selected memory cell is increased therefrom due to deposition of electrons. To read data from the programmed cell, a voltage of about 1V is applied to the drain, a power source voltage (or about 4.5V) is applied to the control gate, and the source is held to the ground voltage. Since the increased threshold voltage of the programmed memory cell acts as an blocking potential to the gate voltage during reading, the programmed cell is considered as an off-cell that has a threshold voltage between 6V and 7V.
Erasing a memory cell is accomplished using the Fowler-Nordheim (F-N) tunneling effect, in which the control gate is coupled to a high negative gate voltage Vg of about -10V and the substrate (or bulk) to a positive bulk voltage Vb of about 5V. Under these conditions, the drain is at a high impedance of floating state. A strong electric field induced by the voltage bias conditions, between the control gate and bulk region, causes the electrons movement into the source. The F-N tunneling typically occurs when an electric field of 6.about.7 MV/cm is developed between the floating gate and bulk region that are separated by the thin insulating film having a thickness of under 100 .ANG.. Since the erased cell has a lower threshold voltage than before the erase operation. It is sensed as an on-cell which has a threshold voltage between 1.about.3V.
Flash memory device include helpful verifying modes used each after programming, erasing, and post-programming operations, so that a distribution profile and cell voltage threshold levels are adjusted to reliable conditions. A first verifying mode is program verifying. Program verifying is conducive to detecting whether threshold voltages of programmed cells are within an expected voltage range. The voltage range is, for instance, higher than 6V as shown in FIG. 2. If the threshold voltage is not within the expected voltage range, the cells might require further programming. If threshold voltages of programmed memory cells are higher than 6V, additional programming is inhibited. In contrast, if the threshold voltages are lower than 6V the cells are further programmed and verified. A second verifying mode is erased verifying. Erase verifying checks whatever erased cells have threshold voltages lower than a predetermined level such as 3V and causes the under-erased cells to be forced into an additional erase mode. As with the program verifying mode, cells having threshold voltages under the 3V after erasing are prevented from the additional erasing operations. Over-erased memory cells are occasionally provided even after the program and erase verifying modes are effectuated. When this happens, an additional verifying mode, i.e., over-erasure verifying, is provided to the flash memory device. The over-erasure verifying mode is accomplished after completing a post-programming operation that cures the over-erased memory cells, in which the post-programming is terminated when threshold voltages of the over-erased memory cells are over the 1V.
While the verifying modes detect whether threshold voltages of the programmed and erased cells are within a predetermined voltage range, reading the memory cells checks whether selected memory cells are on-cells (i.e., erased cells) or off-cells (i.e., programmed cells). A relationship exists between a threshold voltage established by programming and erasing operations and a voltage bias condition set by voltages provided to a gate electrode, drain and source electrodes. Current through a programmed cell is close to zero while current passing through an erased cell is about 20 .mu.A.
FIG. 3 is block diagram of a conventional flash memory device for conducting verifying and reading operations. Main memory cell array 10 and reference cell array 20 are coupled to sense amplifier circuit 30. Main memory cell array 10 is coupled to control circuit 12. Reference cell array 20 is coupled to control circuit 22. Reference cell array 20 is formed of a plurality of reference cells such as cell Rcell0 that is similar to a cell (not shown) of memory cell array 10. When the device is in a verifying mode (the erase verifying, the over-erasure verifying, or the program verifying mode), it is desirable that the current through the reference cell be about equal to the current through the memory cell. Table 1 lists example voltages for the different modes of operation for the device shown in FIG. 3. When the device is in a read mode, however, it is desirable that the current through the reference cell be about half of the current through the memory cell. Since the memory and reference cells are designed to have nearly identical structural sizes, it is necessary to modify the bias condition of the reference cells relative to the memory cell to meet the current requirements.
TABLE 1 Gate voltage of Gate voltage of the Operation mode memory cell (Vg) reference cell (Vgr) Reading 4-5 V 0.7 .times. (4-5 V) Program verifying 6.5 V 3.5 V Erase verifying 3.5 V 3.5 V Over-erasure verifying 2.5 V 4.5 V
Referring to Table 1, the gate voltage Vgr applied to the control gate of reference cell Rcell0 is 0.7.times.Vg (gate voltage of the memory cell) for reading a state of the memory cell. FIG. 4 is a graph of the current and voltage through the memory cell plot A- and the reference cell plot B. As evident in FIG. 4, the selected memory cell can be successfully detected as an on-cell at sensing position P1 but not at positions P2 and P3. The relatively small current margin at sensing position P2 and P3 between the memory cell and the reference cell, make it difficult for a sense amplifier (not shown) to sense and amplify the difference. Although the gate voltage applied to the reference cell is designed to cause the current of the reference cell to be a half of that of the memory cell in a read mode, it may not be easy to control the reference current as it appears at an input of the sense amplifier circuit. That is, the current flowing through the reference ell as it appears at the input of the sense amplifiers varies with variations in an off-set voltage at the input of the sense amplifier circuit variations in operating voltage ranges between the memory cell and reference cell, and the like. The resulting unstable reading conditions might cause reading failures such that a substantial on-cell would be read out as an off-cell.